From Mono-FPGA to Multi-FPGA Emulation Platform for NoC Performance Evaluations
Junyan TAN, Virginie FRESSE, Frederic ROUSSEAU
Electronic Devices, Vol. 3, No. 2, 2014.
DOI: 
Link: http://www.dline.info/ed/fulltext/v3n2/2.pdf
Abstract:
Experimental approaches used for architecture exploration and validation are often based on configurable logic device such as FPGA. NoC architectures require multi-FPGA platforms as the resources of a single FPGA are not big
enough. Partitionning a NoC on multi-FPGA requires special techniques for allocating communication channels, physical links and suitable resource allocation scheme. We present a scalable emulation platform and its associated design flow based on a multi FPGA approach that allows quick exploration, evaluation and comparison of NoC solutions. The efficiency of our
approach is illustrated through the deployment of the Hermes NoC and its exploration on several FPGA platforms.