Heuristic for Accelerating Run-Time Task Mapping in NoC-based Heterogeneous MPSoCs
Mohammed Kamel Benhaoua , AmitKumar Singh, Abou El Hassan Benyamin
Journal of Digital Information Management, Vol. 12, No. 5, 2014.
DOI: 
Link: http://dline.info/fpaper/jdim/v12i5/2.pdf
Abstract:
Multi Processor Systems on Chip (MPSoC)
has emerged as a solution to adress the incremental Computational requirements for future applications. The Network-On-Chip (NoC) has been introduced as a power efficient, scalable inter communication, interconnection mechanism between processors. One important phase in architectural exploration in NOC-based MPSOC is the mapping. The application and architectural are represented
by processing model, application task graph and
architectural graph respectively. Mapping parallelized tasks of applications onto these MPSoCs can be done either at design-time (static) or at run-time (dynamic). Static mapping strategies find the best placement of tasks at
design-time and hence these are not suitable for dynamic workload and seem incapable of run-time resource management. The number of tasks or applications executing in MPSoC platform can exceed the available resources, requiring efficient run-time mapping strategies to meet with this constraints. In this paper, we propose a
new packing strategy to find free resources for run-time mapping of application tasks on NoC-based
Heterogeneous MPSoCs. The proposed strategy
minimizes the task mapping time in addition to placing the communicating tasks close to each other. To evaluate our approach, a comparative study is carried out. Experiments show that our strategy provides better results when compared to latest dynamic mapping strategies reported in the literature.