@article{2195,
  author = {Subin Raj C, Jebasingh Kirubakaran S J, Arulmary A, Senthil Kumar V},
  title = {Look Ahead Clock gating using an Auto gated Flip flop for Low Power Application},
  journal = {Journal of Electronic Systems},
  year = {2017},
  volume = {7},
  number = {1},
  doi = {},
  url = {http://www.dline.info/jes/fulltext/v7n1/jesv7n1_3.pdf},
  abstract = {We propose new technique for clock gating. Clock gating is helpful for reducing power consumed in digital systems. There are three technique used, viz., (i) Synthesis Based method (ii) Data driver Method, and (iii) Auto gated flip flop (AGFF). The Auto gated Flip flop can be distributed in the clock distribution network. Clock distribution uses 
current other than voltage by giving global clock. With auto gated flip flop, it is used for power sowing. Clock gating can be tested in current mode pulsed flip flop which enable urrent-Mode Pulsed Flip-Flop with Enable (CMPFFE) using 48nm CMOS technology. In the  Look Ahead Clock Gating (LACG) computers, the clock signals at one cycle ahead of 
time. The Flip flop depends on the present cycle in LACG. This model can be characterized by power saved in FF. This technique is based on a data to clock togging. Majority of the FF fall in positive Region. Experimentation shows that the industry-scale data displays 22.5% reduction of clock power.},
}