Design of Low Power Preamplifier Latch Based Comparator
Siddharth Bhat, Shubham Choudhary, Jayakumar Selvakumar
Journal of Electronic Systems, Vol. 6, No. 3, 2016.
DOI: 
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Abstract:
This paper presents a pre-amplifier latch based CMOS comparator design. This design is premeditated to be
used as a comparator window. This design is attractive due to its low power dissipation and speed. Preamplifier implies a
cascode structure which stabilizes the output voltage and latch with its regenerative feedback which makes comparison fast
along with detection of small difference between the inputs. The design is simulated in 90-nm CMOS technology using Cadence EDA software. This design provides a low power of 55 ï­W with a speed of 55 MHz and supply voltage of 1.2 V.