Artificial Intelligence-Driven Universal Verification Methodology for Low-Power Semiconductor Design Verification
Yao-Liang Chung
Journal of Electronic Systems, Vol. 16, No. 2, 2026.
DOI: https://doi.org/10.6025/jes/2026/16/2/70-97
Link: https://www.dline.info/jes/fulltext/v16n2/jesv16n2_2.pdf
Abstract:
The increasing complexity of System on Chip architectures has significantly intensified semiconductor
verification challenges. Traditional workflows require extensive manual effort for testcase generation,
constraint extraction, interface interpretation, and validation of complex hardware interactions. Recent
advances in Large Language Models enable automation via long context reasoning, prompt engineering,
and AI assisted test synthesis. This study presents a comprehensive analytical framework for LLM-driven
semiconductor verification using structured prompt orchestration, prompt chaining, semantic context
engineering, and token aware optimisation. The analysis evaluates single shot and multi shot prompting,
hierarchical prompt templates, staged reasoning pipelines, context management strategies, and token
utilization efficiency for complex RTL verification tasks. The framework also investigates long context
processing using Gemini 1.5 based architectures capable of handling large scale SoC repositories without
conventional chunk fragmentation limitations. Comparative evaluation shows that multi shot prompt
orchestration significantly improves reasoning continuity, verification completeness, and hallucination
resistance while enabling scalable handling of interdependent RTL modules. The proposed framework
contributes to scalable AI assisted verification systems for next generation Electronic Design Automation
workflows.