Efficient High Level Methodology for Design, Simulation and Hardware Implementation of Min-Sum LDPC Decoders
Abdessalam Ait Madi, Ali Ahaitouf, Anas Mansouri
Journal of Electronic Systems, Vol. 2, No. 3, 2012.
DOI: 
Link: http://www.dline.info/jes/fulltext/v2n3/3.pdf
Abstract:
In this paper we propose a hardware implementation of a regular (3,6) LDPC decoder. Two processing units corresponding respectively to the variable and Check Node are designed in order to be used in Low Density Parity Check (LDPC) decoding by the Min-Sum Algorithm (MSA). These Units are fully parallel and flexible to be used for different block length when a regular (3, 6) LDPC codes are required. The two proposed units have been first designed and implemented in software by using the high level methodology Simulink tool following a modular design approach. In a second step, these blocks were wired in order to construct a decoder block for the LDPC code (10,5). These units are also described and simulated using Very High Speed integrated circuits Hardware Description Language (VHDL). These three kinds of implementations show that the proposed high level approach is efficient for testing and validating digital circuits before being implemented on desired Field Programmable Gate Array (FPGA) device.