References: [1] Badarov, D., Mihov, G. (2016). Development and Implementation of Digital Phase Locked Loop on Xilinx FPGA, Proceedings of XXV International Scientific Conference Electronics, 80-83 2016. [2] Mihov, G. (2010). Phase and frequency synchronizers, Digital Electronics, Technical University - Sofia, 201-219, October 2010. (in bulgarian) [3] Al-Araji, S. R. (2006). Hussain, Z. M., Al-Qutayri, M. A. (2006). Digital Phase Lock Loops Architectures and Applications, Springer US, 15-30. [4] Shayan, Y. R., Le-Ngoc, T. (1989). All digital phase-locked loop: concepts, design and applications, IEEE Proceedings, 136, Pt. F, No. 1, 1-59, February. [5] Kratyuk, V., Hanumolu, P. K., Moon, U., Mayaram, K. (2007). A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy, IEEE Transactions on Circuits and Systems - II: Express Briefs, 54, (3), 247-251, March. [6] Saber, M., Jitsumatsu, Y., Khan, M. T. A. (2012). A Simple Design to Mitigate Problems of Conventional Digital Phase Locked Loop, Signal Processing: An international journal (SPIJ), 6 (2) 65-77. [7] Djemouai, A., Sawan, M. A., Slamani, M. (2001). New Frequency- Locked Loop Based on CMOS Frequency-to-Voltage Converter: Design and Implementation, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS - II: Analog and Digital Signal Processing, 48 (5) 441- 449, May. [8] Albea, C., Puschini, D., Lesecq, S., Beigne, E., Vivet, P. (2011). Architecture and Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures, Journal of Low Power Electronics, American Scientific Publishers, 328-340. [9] Fernandez, D., Manandhar, S. (2003). Digital Phase Locked Loop, 1-59, December 2003. [10] Xilinx Spartan-3A and Spartan-3A DSP Libraries Guide for Schematic Designs. UG614, (v 13.1), March 2011. |