VLSI Testing using FPGA Devices
M. K. Stojcev, I. Ã…Â½. Milovanovic, E. I. Milovanovic, T. R. Nikolic
Journal of Intelligent Computing, Vol. 13, No. 3, 2022.
DOI: https://doi.org/10.6025/jic/2022/13/3/67-74
Link: https://www.dline.info/jic/fulltext/v13n3/jicv13n3_3.pdf
Abstract:
For VLSI testing, the Built-in-self-text is popularly deployed. To get a high fault coverage in run test vectors, a linear feedback shift register is used to test. In this paper we have used parallel LFSR to experiment the intellectual property blocks with VLSI. The PLFSR is input is linked to apply intest mod test vectors which, possible, detect faults. The proposed PLFSR is implemented FPGA device, and perform at 200 MHz clock frequency and finally produced two random numbers per clock period. The design generated is reconfigurable and can operate with different primitive. he design we have developed shown better trade off performance which has high system throughput and achieve less power consumption.