Journal of Information Organization Vladimir-Alexandru Paun, Bruno Monsuez, Philippe Baufreton 15 3 2025 https://doi.org/10.6025/jio/2025/15/3/113-126 https://www.dline.info/jio/fulltext/v15n3/jiov15n3_1.pdf This paper discusses challenges in modeling and analyzing timing behavior in multi-core processors, particularly focusing on shared resources like caches and buses. It highlights how inter-thread interference and timing anomalies—such as cache misses on one core causing hits on another—complicate Worst-Case Execution Time (WCET) estimation. The document explores methods to address these issues, including code transformations and compile-time techniques to mitigate timing unpredictability. It also emphasizes the importance of accurate processor modeling for real-time systems and addresses limitations in existing documentation regarding verification purposes. Additionally, the paper touches upon timing anomalies in superscalar processors and proposes solutions involving binary modification and instruction injection to achieve deterministic execution behavior. Overall, it stresses the complexity of ensuring timing predictability in multicore architectures for real-time applications.