An Interface Architecture of Source-Synchronous Differential Point-To-Point Parallel Link
Goran Jovanovic, Mile Stojcev, Tatjana Nikolic and Goran Nikolic
Journal of Information & Systems Management, Vol. 12, No. 2, 2022.
DOI: https://doi.org/10.6025/jism/2022/12/2/52-60
Link: https://www.dline.info/jism/fulltext/v12n2/jismv12n2_3.pdf
Abstract:
To transmit parallel data is normally we use clock across printed circuit board so that the skew problem is addressed. The issue is that the phase relation of the data and clock can be a failure due to different travel times through the link. We fixed the issue with an interface architecture of source-synchronous differential point-to-point parallel link. We used in this work an effective clock de-skew structure based on Delay Locked Loop. It is applied in the BiCMOS technology and is described with a low successful case locking time 40 ns (20 cycles @ 500 MHz), with other features.