@article{2989,
  author = {Joseph R Laracy},
  title = {An RSA Co-processor Architecture Suitable for a User-Parameterized FPGA Implementation},
  journal = {Journal of Information Security Research},
  year = {2020},
  volume = {11},
  number = {2},
  doi = {https://doi.org/10.6025/jisr/2020/11/2/46-53},
  url = {https://www.dline.info/jisr/fulltext/v11n2/jisrv11n2_2.pdf},
  abstract = {This paper describes an original and straightforward architecture for a logic circuit implementation of the RSA
algorithms. The architecture is ideal for teaching advanced undergraduate or graduate students topics associated with
public-key cryptography and digital system design. The system is designed with VHDL for execution on a FPGA. Software
implementations of RSA running on standard PCs are relatively slow as standard microprocessors are not optimized for the
operations RSA must carry out. A key aspect of this approach is the use of Montgomery Multiplication, a method for performing
fast modular multiplication.},
}