An RSA Co-processor Architecture Suitable for a User-Parameterized FPGA Implementation
Joseph R Laracy
Journal of Information Security Research, Vol. 11, No. 2, 2020.
DOI: https://doi.org/10.6025/jisr/2020/11/2/46-53
Link: https://www.dline.info/jisr/fulltext/v11n2/jisrv11n2_2.pdf
Abstract:
This paper describes an original and straightforward architecture for a logic circuit implementation of the RSA
algorithms. The architecture is ideal for teaching advanced undergraduate or graduate students topics associated with
public-key cryptography and digital system design. The system is designed with VHDL for execution on a FPGA. Software
implementations of RSA running on standard PCs are relatively slow as standard microprocessors are not optimized for the
operations RSA must carry out. A key aspect of this approach is the use of Montgomery Multiplication, a method for performing
fast modular multiplication.