@article{1165,
  author = {Ihsen BEN MBAREK, Dhia BELHAJALI, Mohamed MAZOUZI, Salem HASNAOUI, Khaled JALASSI},
  title = {Network on Chip Scheduling Modified i-SLIP Scheduler for High-Speed Virtual Output Queuing Packets},
  journal = {Progress in Signals and Telecommunication Engineering},
  year = {2013},
  volume = {2},
  number = {1},
  doi = {},
  url = {http://www.dline.info/pste/fulltext/v1n1/1.pdf},
  abstract = {This paper presents a design and an implementation of a hardware scheduler in VHDL for High-Speed VoQ using a modified i-SLIP algorithm. The aims for the scheduling algorithm is to match input queues with output queues to achieve the maximum throughput while maintaining stability and eliminating starvation. The N-input by N-output scheduler manages VoQ packets to avoid a HOL blocking. This implementation requires N Grant Arbiters, N Accept Arbiters, three input-to-output Swizzles and a FSM. The Modified i-SLIP arbiter requires perforce a state pointer for the highest priority input (or output). The simulation and synthesis results are shown for N = 8. The design was implemented in VHDL RTL, simulated with Modelsim 6.2 and synthesized using Xilinx-ISE and the Virtex-4 device XC4VFX100-12FFG1517 of 90 nm technology to achieve a maximum frequency of 265.88 MHz, a minimum slices utilization of 771 and a total estimated power consumption about 915 mW.},
}