Abstract This paper discusses challenges in modeling and analyzing timing behavior in multi-core processors, particularly focusing on shared resources like caches and buses. It highlights how inter-thread interference and timing anomalies—such as cache misses on one core causing... This paper discusses challenges in modeling and analyzing timing behavior in multi-core processors, particularly focusing on shared resources like caches and buses. It highlights how inter-thread interference and timing anomalies—such as cache misses on one core causing hits on another—complicate Worst-Case Execution Time (WCET) estimation. The document explores methods to address these issues, including code transformations and compile-time techniques to mitigate timing unpredictability. It also emphasizes the importance of accurate processor modeling for real-time systems and addresses limitations in existing documentation regarding verification purposes. Additionally, the paper touches upon timing anomalies in superscalar processors and proposes solutions involving binary modification and instruction injection to achieve deterministic execution behavior. Overall, it stresses the complexity of ensuring timing predictability in multicore architectures for real-time applications. Read More Read Less

Abstract The attached file presents a framework for analyzing and predicting the reliability of context-aware systems, particularly focusing on elder care applications. It integrates model checking and testing techniques to evaluate system correctness and reliability under various scenarios.... The attached file presents a framework for analyzing and predicting the reliability of context-aware systems, particularly focusing on elder care applications. It integrates model checking and testing techniques to evaluate system correctness and reliability under various scenarios. The approach involves constructing a Markov Decision Process (MDP) model, performing reachability analysis, and conducting sensitivity analysis to identify critical components affecting system reliability. Experimental results demonstrate the effectiveness of the framework in detecting bugs and analyzing reliability distribution across components like sensors and networks. The study also highlights practical applications in real-world settings, such as monitoring activities and delivering timely reminders to users. Overall, the work provides a comprehensive method for improving the dependability of context-aware systems through formal verification and quantitative evaluation. Read More Read Less

Abstract The paper examines the penalty method for generating alternative routes in road networks, which has historically been limited by its slow implementation. Leveraging modern techniques like Customizable Route Planning (CRP), the authors achieve efficient real-time processing through... The paper examines the penalty method for generating alternative routes in road networks, which has historically been limited by its slow implementation. Leveraging modern techniques like Customizable Route Planning (CRP), the authors achieve efficient real-time processing through parallelism and vectorization. The penalty method iteratively computes shortest paths, applying penalties to arcs on each path to encourage diverse alternatives. Enhancements include dynamic level selection in CRP to balance query and update costs and modified penalization schemes for faster convergence. Experimental results demonstrate significant speed improvements over classical methods, achieving performance that is up to multiple orders of magnitude faster. The quality of alternative routes is evaluated using metrics like limited sharing, uniformly bounded stretch, and local optimality. The study confirms the viability of the penalty method for interactive applications, offering structurally diverse routes compared to via-node approaches. Despite progress, challenges remain in optimizing runtime and establishing generalized criteria for high-quality alternative routes. Read More Read Less