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Journal of Information & Systems Management (JISM)

An Interface Architecture of Source-Synchronous Differential Point-To-Point Parallel Link

Goran Jovanovic, Mile Stojcev, Tatjana Nikolic and Goran Nikolic
University of NiÃ…Â¡ Faculty of Electronic Engineering NiÃ…Â¡, Serbia

Abstract: To transmit parallel data is normally we use clock across printed circuit board so that the skew problem is addressed. The issue is that the phase relation of the data and clock can be a failure due to different travel times through the link. We fixed the issue with an interface architecture of source-synchronous differential point-to-point parallel link. We used in this work an effective clock de-skew structure based on Delay Locked Loop. It is applied in the BiCMOS technology and is described with a low successful case locking time 40 ns (20 cycles @ 500 MHz), with other features.

Keywords: Differential Interface, Clock Skew, Transmission Line, DLL

DOI:https://doi.org/10.6025/jism/2022/12/2/52-60

Full_Text PDF 1.78 MB Download: 97 times

References:

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[3] Ryu, K., Jung, D.H. & Jung, S.-O. (2012). A DLL with dual edge triggered phase detector for fast lock and low jitter clock generator. IEEE Transactions on Circuits and Systems, 59, 1860–1870 [DOI: 10.1109/TCSI.2011.2180453].
[4] Yeung, E., Horowitz, Mark. (2000). A 2.4 Gbps/Pin Simultaneous Bidirectional Parallel Link with Per-Pin Skew Compensation, IEEE Fount & of Solid-State Circuits, Vol. 35, pp. 1619–1628.
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[6] Nikolic, G. & Jovanovic, G., Stojcev, M. & Nikolic, T. (2017) Precharged phase detector with zero dead-zone and minimal blindzone. Journal of Circuits, Systems and Computers, 26, 1750179 (16 pages) [DOI: 10.1142/S0218126617501791].
[7] Jovanovic, G.S. & Stojcev, M.K. (2006) Current starved delay clement with symmetric load. International Journal of Electronics, 93, 167.175.
[8] HIP-Microelectronics SiGe:C BiCMOS technologies for MPW & prototyping. https:// www.ihp-microclectronics.com/en/ servicesImpw-prototyping/sigerebiernos-technologiechtml.

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