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[5] Damphousse, S. (2016). How to estimate the phase noise of a PLL with basic datasheet specifications, Texas Instruments, March 2, 2016, https://e2e.ti.com/blogs_/b/analogwire/archive/2016/03/02/understanding-datasheet-phase-noise-specificationsof- a-phaselocked-loop?DCMP=lmx25x2&HQS=sva-sds-fcp-lmx25x2-exah-null-null-eu
[6] Banerjee, D. (2006). PLL Performance Simulation and Design Handbook - 4th Edition, 13 October 2006
[7] WEBENCH Clock Architect, TI, http://www.ti.com/lsds/ti/analog/webench/clock-architect.page
[8] WEBENCH Design Center, TI, http://www.ti.com/lsds/ti/analog/webench/overview.page?DCMP=sva_webench &HQS=webench-btechday
[9] Orcad Design Suit 16.6, Users’ Guide, Cadence, 2014 216. |
