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Research on Power Attack Comprehensive Experiment Platform Based on SAKURA - G Hardware Circuit
GeJiao, DeXinDing, Lang Li
School of Environment Protection and Safety Engineering, University of South China, Hengyang Hunan 421001, China & College of Computer Science and Technology, Hengyang Normal University, Hengyang Hunan 421002, China
Abstract: The power attack of the hardware circuit is going through the steps of the algorithm write in FPGA, power consumption, data processing and analysis and the existing power attack experiment platform is too decentralized for each step, where the operation is complex, requiring a high degree of integration of the experimental platform for support. The development of a hardware circuit based on power attack comprehensive experimental platform SAKURA-G, realized these steps will be integrated into a platform, simplify the operation process, to ensure the accuracy of power acquisition, and realizes parallel data processing, improve the accuracy and efficiency of power attack.
Keywords: SAKURA-G, Power Attack Experiment Platform, AES, CPA Research on Power Attack Comprehensive Experiment Platform Based on SAKURA - G Hardware Circuit
DOI:https://doi.org/10.6025/jes/2019/9/3/102-111
Full_Text   PDF 4.8 MB   Download:   378  times
References:
[1] Kocher, P., Jaffe, J., Jun, B. (1999). Differential power analysis. International Cryptology Conference on Advances in Cryptology. Berlin:Springer-Verlag, 1999, 388-397.
[2] Wei-dong, ZHONG., Qing-quan, MENG., ZHANGShua-wei. (2017). Implementation and optimization of S-box on AES Based on secret sharing. Advanced Engineering Sciences, 01, 191-196.
[3] YueDaheng. (2011). Research on circuit-level design against power analysis attack for cryptographic chip, National university of Defense Technology.
[4] LI Lang, LI Ken-li, JIAOGe. (2012). Research of power analysis physical experiment platform based AT89C51, Application Research of Computers, 07, 2681-2682.
[5] Li Zonghua. (2016). Design and implementation of differential power analysis attack platform, South China University of Technology.
[6] Bilgin, B., Gierlichs, B., Nikova, S. (2014). A more efficient AES threshold implementation. Progress in Cryptology-FRICACRYPT 2014. Switzerland: Springer, 2014 267-284.
[7] HU Wen-jing, WANGAn., Wu Li-ji. (2015). Power attack of SM4 hardware implementation based on SAKURA-G board, Microelectronics & Computer, 04, 15-20.


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