Abstract In this work we have presented the review of association memory methods and their usability. Besides, we have presented the file cabinets systems used. We have also detailed the system of managing elements for file cabinets. The required system application is implemented to achieve the goals. The system we have developed enable to manage the queue elements and can impact... In this work we have presented the review of association memory methods and their usability. Besides, we have presented the file cabinets systems used. We have also detailed the system of managing elements for file cabinets. The required system application is implemented to achieve the goals. The system we have developed enable to manage the queue elements and can impact on the memory tools to ensure efficiency. Read More Read Less

Abstract We have developed a multicore architecture to support the geospatial data management. For the multicore processing and using Geographic Information Systems, we have used parallel processing based on the application of Open Multi Processing. This will help to improve the use of map-matching computing system for the large spatial datasets with road segment networks. The algorithm designed is useful for... We have developed a multicore architecture to support the geospatial data management. For the multicore processing and using Geographic Information Systems, we have used parallel processing based on the application of Open Multi Processing. This will help to improve the use of map-matching computing system for the large spatial datasets with road segment networks. The algorithm designed is useful for performance of multicore system. We have conducted testing and found that the high performance computing in geographical information system is possible for validation. Read More Read Less

Abstract For VLSI testing, the Built-in-self-text is popularly deployed. To get a high fault coverage in run test vectors, a linear feedback shift register is used to test. In this paper we have used parallel LFSR to experiment the intellectual property blocks with VLSI. The PLFSR is input is linked to apply intest mod test vectors which, possible, detect faults. The... For VLSI testing, the Built-in-self-text is popularly deployed. To get a high fault coverage in run test vectors, a linear feedback shift register is used to test. In this paper we have used parallel LFSR to experiment the intellectual property blocks with VLSI. The PLFSR is input is linked to apply intest mod test vectors which, possible, detect faults. The proposed PLFSR is implemented FPGA device, and perform at 200 MHz clock frequency and finally produced two random numbers per clock period. The design generated is reconfigurable and can operate with different primitive. he design we have developed shown better trade off performance which has high system throughput and achieve less power consumption. Read More Read Less