| References: [1] Fatin, Gh.Z. & Kanani, Z.D.K. (2008) A very low power bandpass filter for low-IF applications. Journal of Circuits, Systems and Computers, 17, 685–701 [DOI: 10.1142/S0218126608004496].
[2] Chang, Z.Y., Haspeslagh, D. & Verfaillie, J. (1997) A highly linear CMOS Gm-C bandpass filter with on-chip frequency tuning. IEEE Journal of Solid-State Circuits, 32, 388–397.
[3] Changsik Yoo, Seung-Wook Lee & Wonchan Kim (1998) A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning. IEEE Journal of Solid-State Circuits, 33, 18–27 [DOI: 10.1109/4.654933].
[4] Maneatis, J.G. (1996) Low-jitter process-independent DLL and PLL based on self-biased techniques. IEEE Journal of Solid- State Circuits, 31, 1723–1732 [DOI: 10.1109/JSSC.1996.542317].
[5] Stojcev, M. & Jovanovic, G. (2008) Clock aligner based on delay locked loop with double edge synchronization. Microelectronics Reliability, 48, 158–166 [DOI: 10.1016/j.microrel.2007.02.025].
[6] IHP-microelectronics, SiGe:C BiCMOS technologies for MPW & prototyping. www.ihp-microelectronics.com/16.0.html.
[7] 15, Jovanovic, G. & Mitic, D. (2013) M. Stojcev and D. Antic, Self- Tuning Biquad Band-Pass Filter, Journal of Circuits, Systems, and Computers, World Scientific Publishing Company, 22, 1–19.
[8] Leroux, P., Steyaert, M. & Lna, E.S.D. (2005). Co-design for Fully Integrated CMOS Wireless Receivers. Springer: Dordrecht. |
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