Volume 06 Number 2 July 2016

    
Power Reduction Technique for Data Encoding in Network-on-Chip (NoC)

Venkatesh Rajamanickam, M.Jasmin

https://doi.org/

Abstract The power dissolute by the links of a network-on-chip (NoC) starts to play with the power dissipated by the additional basic elements of to the communication sub-system within specifically, the routers &network interfaces (NIs). In this, we present a conventionaldata encoding schemes meant to reducing the dissipated of power by the links in the NoC. The proposed schemes are universal and transparent with... Read More


A Low Power and High Speed Pipeline Architecture using adaptive Median Filter for Noise Reduction in image Processing

S. Nirmal Raj, S. Ashok, P. Bala Vengateswarlu, G.Vishnu Vardhan Rao

https://doi.org/

Abstract Low level data processing purposes are like FIR filtering, recognition of patterns or correlation, whereas the parallel implementation is upheld bythe design matched distinct intention arithmetic; elevated throughput FPGA routes facilely output waveform even for the most advanced DSP processors. In this paper the examination of a high-speed non-linear Adaptive median filter implementation is presented. Next the Adaptive Median Filter solves the dual... Read More